This invention relates to integrated circuits; and more particularly, it relates to the manufacture of integrated circuits with a planar topography.
In the prior art, it is customary to fabricate integrated circuits on a thin flat semiconductor substrate called a wafer. During this fabrication, transistors are formed in the top surface of the substrate, and alternating layers of insulating material and patterned signal conductors are formed over the top surface in order to interconnect the transistors together.
A problem, however, with the above described prior art integrated circuit is that as the layers of insulating material and signal conductors are added to the circuit, the topography of the circuit becomes more and more nonplanar. When a cross section of the wafer is viewed under a microscope, each insulating layer will have peaks and valleys; and the signal conductors will go up and down o those peaks and valleys.
Each layer of signal conductors is formed from an unpatterned conductive layer by covering it with a layer of photoresist, and exposing the photoresist to light through a mask. However, the accuracy with which the mask's image can be transferred to the photoresist decreases as the nonplanarity of the photoresist increases. Why this is will now be explained with the help of FIG. 1.
There, reference numeral 10 indicates a semiconductor wafer; reference numeral 11 indicates a layer of photoresist on an unpatterned conductive layer; reference numeral 12 indicates a mask whose image is to be replicated in the photoresist; and reference numeral 13 indicates light which is passed through the mask to expose the photoresist. As this light passes through the mask, it diverges, as is indicated, for example, by reference numeral 13a; and a lens 14 is provided between the mask and the wafer in order to focus the light on the photoresist.
If, however, the unpatterned conductive layer and the overlying photoresist are nonplanar, then the mask image will not be accurately focused on the entire surface of the photoresist. When the lens 14 is positioned such that the mask image is accurately focused on the peaks of the photoresist 11, then the mask image will be out of focus on the valleys of the photoresist; and vice versa. This problem is herein called the depth of focus problem.
After the exposed portions of the photoresist are removed, the remaining photoresist patterns will have sharply defined (vertical) edges where the mask image was accurately focused. This is indicated by reference numeral 11a. Conversely, the remaining photoresist patterns will have rounded edges as is indicated by reference numeral 11b where the mask image was not accurately focused.
Since the edges of the photoresist cannot be accurately patterned over the entire surface of the wafer, it follows that the width of the corresponding signal conductors also cannot be accurately patterned. And, this in turn limits the density with which signal conductors can be fabricated.
Accordingly, a primary object of the invention is to provide an improved integrated circuit in which the insulating layers and interleaved signal conductors are substantially planar.